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So basically you just make a couple memory reads a few hundred thousands times and this will alter some near cell? why manufacturers didn't test this? it looks like a pretty obvious thing to test while working at these scales.


b/c the applications that care the most about these types of errors (big iron networking, and mil/aero) implement software error correction in the processor. It's not worth spending the extra money in final test when commodity DRAM is, well, a commodity.


Yes, ECC memory, although it's mostly implemented by the chipset and DRAM modules, with only a small part of it being in the processor.


Thanks for the clarification John.


commodity DRAM is, well, a commodity.

You're essentially saying that producing DRAM that doesn't work like memory should, regardless of access pattern, is excusable because it's "commodity"?




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