Isn't the reset synchronous? (Small Quibble) Agreed that hardware language is ge...

		owenfi on Sept 8, 2013 \| parent \| context \| favorite \| on: Why hardware development is hard: Verilog is weird Isn't the reset synchronous? (Small Quibble) Agreed that hardware language is generally hard to pick up on but "produced something random" is a bit strong (excluding bugs in simulators, which are a bit more common than I would've expected).