Fair point about the protection structures lagging non-linearly in equivalent process node. Though wouldn't CDM events still correlate with feature density since the charge distribution across the die (assuming it correlates with the total gate capacitance)? More gates (higher density) means more to discharge safely?

Actually, for latchup specifically - even with oversized protection, don't the triggering conditions get worse with scaling since the parasitic SCR structures in the core have tighter spacing?