Ok, maybe that's not clear, probably my not-so-perfect English is a problem.
The dataflow architecture was the initial idea. What I'm talking about now is the ternary processor, a normal VonNeumann processor with ternary data and ternary arithmetic.
This may eventually form the basis for the dataflow processor, but right now I'm talking about and building the ternary processor (Of course dataflow architectures are quite different and unconventional, but that's in the future, I'm not talking about it now).
As for address management, as I said the mainboard does it all, but I didn't care to go that low in detail, it's all a simple VHDL function in an FPGA.
It already comes to the FPGA in "ternary encoded bunary" from external circuits.
While not quite as terrible as my first idea, I suspect this simple function expands into much more logic than is reasonable, both in terms of size and propagation delay - the rest of the system is just small and low speed enough that you don't notice it.
The way I see it, cool hobby project, except you've already created a website promising next generation AI supercomputer chips, and then basically admit that you don't even know what goes on at the level of logic gates. And seem to avoid giving any technical details at all.
Designing a high-performance CPU is difficult enough to do in conventional binary logic, and is generally done by teams of people who know much more than you or I about all sorts of details on how to pipeline instruction execution efficiently, with branch prediction and speculative execution etc., and also the constraints imposed by manufacturing processes and physics itself.
You can't just assume someone can magically turn your ideas into such a CPU. And if they could, they could probably do it without you and whatever intellectual property you seem to be wanting to keep secret. Also, ternary being considered more efficient in some mathematical way doesn't necessarily mean an actual hardware implementation will be similarly efficient.
ok, now i can say for sure, you didn't read the site well at all. you didn't even read my answers well. maybe you would have understood that now mosfet level design is already happening but it only concerns the CPU (if you want to deal with the mainboard, fine, you will have read that it is open hardware). I don't understand what you need such low level technical details for, it is obvious that i am not here to share them. If you want to make a CPU do it too, in the end we will see who did it better. now excuse me I have some serious work to do.
Maybe it's a problem with my reading comprehension (or my web browser), but there seems to be no information about this open hardware - or really anything technical, other than the CPUs bus width and register count -, on your site or forum?
As for address management, as I said the mainboard does it all, but I didn't care to go that low in detail, it's all a simple VHDL function in an FPGA. It already comes to the FPGA in "ternary encoded bunary" from external circuits.