I'm sure the front end has had a lot of work and cleverness put into it, and I'm sure that it's able to, say, correctly guess where instruction boundaries are more than 99% of the time without knowing for sure and then remove those instructions from the queue if it turns out that the guess was wrong. But that just means that 4-wide decode is only on the same order of power consumption as execution, instead of being an order of magnitude more like if you'd done thing the naive way. I'm sure that the work they do _is_ stunning, but its work that doesn't even have to be done on more regular instruction sets.
It's not a problem with being variable length or CISC, its a problem with the lack of self-synchronization. If you, say, had 8 or 16 bit blocks were first bit of each block told you whether it was the beginning of an instruction you wouldn't have this problem at all. I'd generally say that for a modern general purpose computer variable length instructions and a large number of op-codes are a good idea, though a large number of addressing modes seems to still be a disadvantage. Its probably no accident that ARM, the "CISCiest" of the RISC processors is so popular right now.
It's not a problem with being variable length or CISC, its a problem with the lack of self-synchronization. If you, say, had 8 or 16 bit blocks were first bit of each block told you whether it was the beginning of an instruction you wouldn't have this problem at all. I'd generally say that for a modern general purpose computer variable length instructions and a large number of op-codes are a good idea, though a large number of addressing modes seems to still be a disadvantage. Its probably no accident that ARM, the "CISCiest" of the RISC processors is so popular right now.