> you're getting beaten over the head by chip designers telling you that your future cpu is going to consist of a (possibly large) array of processing cores with a high-capacity bus connecting them. they are telling you this is the only way they can give you higher performance. you had better start believing them because these systems are starting to get delivered now.
If your chip designers are telling you that they're building a large array of procesing cores connected with a high-capacity bus, you need to get some new chip designers.
If you've got a bus that can actually support a modest number of cores, your cores are too wimpy and should be built with whatever was used for the bus.
More likely, you actually have a saturated bus that is the system bottleneck, so your cores are spending most of their time waiting for access.
There is no silver bullet. Many problems are bound by bisection bandwidth. The more cores, the worse the problem. You end up devoting proportionally more space and power to communication as you increase the number of processors.
If your chip designers are telling you that they're building a large array of procesing cores connected with a high-capacity bus, you need to get some new chip designers.
If you've got a bus that can actually support a modest number of cores, your cores are too wimpy and should be built with whatever was used for the bus.
More likely, you actually have a saturated bus that is the system bottleneck, so your cores are spending most of their time waiting for access.
There is no silver bullet. Many problems are bound by bisection bandwidth. The more cores, the worse the problem. You end up devoting proportionally more space and power to communication as you increase the number of processors.