I haven't fully read through the article yet, but on the topic of FIFO-based models of computation, there are queue automatons and Post-Tag systems:

[0] https://en.wikipedia.org/wiki/Queue_automaton [1] https://en.wikipedia.org/wiki/Tag_system

This reminds me of a CPU architecture that Bill Wulf did back in the late 80's.

http://digitalcollections.library.cmu.edu/awweb/awarchive?ty...

It had some really interesting ideas for hiding latency.